The present invention relates to the field of bipolar integrated circuits, and more particularly to avalanche diodes designed to serve as voltage references in such circuits.
Avalanche diodes have been thoroughly studied, and it is known, when discrete components are achieved, how to obtain satisfactory avalanche diodes. However, when manufacturing integrated circuits, numerous requirements are to be met, namely, a large number of elementary components are simultaneously achieved and all these components have to be achieved with a minimum number of manufacturing steps.
FIG. 1 is intended to review the main technological steps and structures achievable in a bipolar integrated circuit. Such a circuit is generally achieved on a substrate 1 of a first (generally P) conductivity type, on which is formed an epitaxial layer 2 of a second conductivity type (N). At the interface between the substrate 1 and the epitaxial layer 2 can be formed N.sup.+ -type buried layers, resulting from a dopant implantation carried out in the substrate prior to epitaxial growth. The epitaxial layer is divided into wells by P.sup.+ -type deep diffused regions 5 or by regions 6 with shallower diffusions extending from the surface and joining regions 7 resulting from a P-type implantation in the surface of the substrate 1 prior to epitaxy. In each well, provided or not with a buried layer, it is then possible to form various types of components. The prevalent component is the NPN transistor comprising a P region 10 corresponding to the base of an NPN transistor. Inside this P region 10 is formed an N.sup.+ -type region 11 corresponding to the transistor emitter. These P and N.sup.+ diffusions, 10 and 11, respectively, can be used in structures other than an NPN transistor. However, they are still called, when it is desired to designate their nature and their doping type, P base diffusions for the regions formed simultaneously with the base and N emitter diffusions for regions formed simultaneously with the emitters of the NPN transistors. For example, the collector contact of the NPN transistor is achieved on an N.sup.+ region 12 which is an N emitter diffusion. Moreover, as shown in the right-hand portion of FIG. 1, P.sup.+ -type regions 13 are generally provided, serving, for example, as emitter and collector for PNP power transistors.
To sum up, from the surface of an N type well, it is possible to form:
a first P-type region corresponding to the base of the NPN transistors, PA1 second P-type region corresponding to the emitters of the PNP transistors, PA1 a third P-type region corresponding to an insulation diffusion (entire insulation diffusion such as diffusion 5 or partial insulation diffusion such as diffusion 6), PA1 an N.sup.+ -type diffusion corresponding to the emitters of the NPN transistors. PA1 r designates the resistance per square of the P layer 22,
A priori, it is possible to form avalanche diodes by reversely biasing a junction formed from two regions of opposite type among the above regions.
In practice, one of the avalanche diode structures which gives the most satisfactory results is a structure of the type illustrated in the cross section view of FIG. 2A and in the top view of FIG. 2B. This avalanche diode is formed in an N well 20 (the underlying P substrate is not shown). The avalanche diode comprises an N.sup.+ emitter region 21 formed in a P base region 22. Substantially in the middle of region 21 a highly doped P diffusion 23 has been previously formed, so that it is the interface between the N region 21 and the P region 23 which corresponds to the junction liable to provide the avalanche effect. This is intended to provide on both sides of the junction substantially homogeneous concentrations of N dopant and P dopant so that the avalanche surface is clearly defined. Indeed, in the absence of region 23, the avalanche junction would be the junction between region 21 and region 22. Since the P region 22 has been obtained through diffusion, its doping level is higher at the surface than depthwise and the avalanche would tend to occur preferably near the surface, which causes numerous drawbacks as regards the definition of the junction surface liable to be set to avalanche mode and as regards the characteristics of the avalanche junction since the upper surfaces of a layer are the most likely to be polluted and damaged with age. Indeed, moving electrical charges may happen to be in the oxide coating the junction surfaces. The presence of these charges changes the avalanche conditions, causing excessive noise and often a change in time of the avalanche voltage value.
Of course, the N.sup.+ region 21 is substantially more highly doped than the P.sup.+ region 23 so that all this N.sup.+ region has substantially the same doping level, even where the upper portion of P.sup.+ region 23 was formed. The P.sup.+ region 23 can, for example, correspond to a P emitter region of the PNP transistor or to a P insulation region. A metallization 24 is provided on the N region 21 and a metallization 25 is provided on the apparent surface of the P region 22.
Thus, the described structure provide a satisfactory definition of the avalanche voltage. Preferably, the area of the junction between layers 21 and 23 is as small as possible so that the current density in this diode is relatively high, which provides a more reliable definition (less noisy) of the avalanche voltage, necessary for defining a reference voltage. However, a drawback of this structure is that the avalanche current will flow through the annular portion of P region 22, designated by resistance R.sub.1, pinched between the N.sup.+ diffusion 21 and the epitaxial layer 20. This pinched region has a relatively high resistance which is defined with a relative inaccuracy and which depends upon the accuracy of the relative positioning of regions 21 and 23. Hence, the avalanche voltage which is accurately defined at the junction between regions 21 and 23 is less accurately defined between electrodes 24 and 25 due to the presence of the access resistance R.sub.1. If the structure is ring-shaped as shown in the top view of FIG. 2B, the resistance of the above pinched region will be: EQU R.sub.1 =r/2.pi. Log(d2/d1)
where
d1 designates the diameter of the junction region between layers 21 and 23, and
d2 designates the diameter of the substantially horizontal junction region between regions 21 and 22.
In order to reduce the value of R.sub.1, d1/d2 should approach 1. However, it is not possible to freely select these values because they are imposed by the fact, on the one hand, that the diameter d1 has to be as small as possible to obtain a high current density at the junction to prevent the avalanche diode from being noisy and, on the other hand, that the difference between values d1 and d2 is fixed by technological parameters and especially by the positioning accuracy of two successive masks.
Thus, an object of the invention is to provide a new avalanche diode structure implementable in an integrated circuit and using no additional manufacturing steps other than the steps normally provided for in a bipolar integrated circuit, this structure being such that the access resistance to the avalanche diode is reduced.